Edward W. Carstens

12/92,BS,EE,UMR(Univ.Missouri- Rolla),GPA3.64/4.00,

Over four years of experience in digital design.
Designed digital encoder for high-speed graphics cable transmission,
starting with behavioral Verilog, synthesizing (using Ambit) with
timing constraints, and verification.
Responsible for the RTC, SBI, and SCI modules (written in Verilog
and VHDL) for a power management chip.  Synthesized logic using
Ambit and Synopsys tools.  Simulated using Verilog-XL, Leapfrog VHDL,
and Analog Artist tools.  Transistor-level experience using Mentor
and Cadence tools.  Also provided software support for team (Skill).
Wrote Perl scripts to generate input files for a standardized
design database used for flip-chip base array packages.
Responsibilities under a DSP project included installation of
initial database, verification methodology, and subsequent model
changes under custom version control system. Converted original CPU
testcases to run on a development version of the DSP.  Supported the
team development of DSP test cases by creating programs to simplify
test case verification.  Broad experience in C++, UNIX, Pascal,
Assembly, Lisp, Skill, and Perl.  Tools experience includes
Cadence Virtuoso, Cadence Composer, Mentor Graphics Tools, Synopsys,
Leapfrog VHDL, Verilog-XL, and Analog Artist.8/93 - 5/94, U. Florida. Teaching Assistant.
5/89 - 12/89, IBM Rochester, AS/400 Operating System Tester.
Developed program to keep tabs on system configuration used
for testing. Worked on automating the testing process.

8/87 - 8/88, Nat'l Merit Scholar.
Curator and Bright Flight Awards.
Chancellor's Leadership Class.
Tau Beta Pi and Phi Eta Sigma Honor Societies.
Argonne Nat'l Labs Undergraduate Symposium Participant.
2nd place in Sigma Xi Technical Paper Contest.

Jim Coker
Steven Daniel

To glorify God in all I do, to make every moment count, and
to take as many souls with me to heaven as possible.